1. Field of the Invention
The present invention relates to a reference voltage generating circuit mounted on a semiconductor integrated device for generating a reference voltage that exhibits little fluctuation caused by external variations.
2. Description of the Related Art
In semiconductor integrated devices, there is a risk that circuit operation within the semiconductor integrated device may undergo changes due to fluctuations in the outside power supply voltage or outside temperature. In analog circuits in particular, external fluctuations may cause unstable circuit operation, resulting in malfunctioning. A reference voltage having little fluctuation caused by external variations is therefore essential. One example of a reference voltage generating circuit for generating a reference voltage that is relatively unaffected by external fluctuation is described in Japanese Patent Laid-open No. 296491/89.
FIG. 1 shows a circuit diagram of this type of reference voltage generating circuit of the prior art.
This reference voltage generating circuit comprises p-channel MOS transistors 11-13, n-channel MOS transistors 21-24, 45, and 46, and resistor 1.
P-channel MOS transistor 11 has its source connected to power supply voltage VCC and its gate connected to reference voltage generating circuit activating signal BVREF. In this case, reference voltage generating circuit activating signal BVREF is low-level (hereinbelow abbreviated "L") when activating the reference voltage generating circuit and high-level (hereinbelow abbreviated "H") when deactivating the reference voltage generating circuit. Resistor 1 is connected between the drain of p-channel MOS transistor 11 and the drain of n-channel MOS transistor 23. N-channel MOS transistor 23 has its gate and drain connected together, and has its source connected to ground. N-channel MOS transistor 21 has its gate connected to the gate of n-channel MOS transistor 23, thereby constituting together with n-channel MOS transistor 23 a current mirror circuit.
P-channel MOS transistor 12 has its gate and drain connected together, and has its source is connected to VCC, and has its drain connected to the drain of n-channel MOS transistor 21. P-channel MOS transistor 13 has its source connected to VCC, and its gate connected to the gate of p-channel MOS transistor 12, thereby constituting together with p-channel MOS transistor 12 a current mirror circuit. N-channel MOS transistor 45 has its drain connected to the drain of p-channel MOS transistor 13, and its gate and drain connected together. N-channel MOS transistor 46 has its drain connected to the drain of p-channel MOS transistor 13, its gate and drain connected together, and its source connected to ground. The threshold voltages of n-channel MOS transistors 45 and 46 are set to differing values, designated VT.sub.45 and VT.sub.46, respectively. N-channel MOS transistor 22 has its drain connected to the source of n-channel MOS transistor 45, its source connected to ground, and its gate connected to the gate of n-channel MOS transistor 23. The gate width of n-channel MOS transistor 22 is set to one-half that of n-channel MOS transistors 21 and 23 since that when the gate voltage is the same, one-half the current of n-channel MOS transistors 21 and 23 flows across the drain and source.
In the prior-art reference voltage generating circuit, the source voltage of n-channel MOS transistor 45 is obtained as reference voltage VREF.
N-channel MOS transistor 24 has its gate which reference voltage generating circuit activating signal BVREF is applied to, its source grounded, and its drain connected to the gate of n-channel MOS transistor 23.
N-channel MOS transistor 24 serves to render the gate voltage of n-channel MOS transistors 21, 22, 23 L when the operation of the reference voltage generating circuit is halted at the time reference voltage generating circuit activating signal BVREF has become H.
The operation of the reference voltage generating circuit of the prior art will be explained below.
To operate the reference voltage generating circuit, reference voltage generating circuit activating signal BVREF is first rendered L to turn on p-channel MOS transistor 11 and turn off n-channel MOS transistor 24.
Current I, which is determined by resistor 1 and n-channel MOS transistor 23, then flows across the drain and source of n-channel MOS transistor 23 to generate voltage V.sub.1, which is a voltage lower than power supply voltage VCC. The voltage V.sub.i is applied to the gate of n-channel MOS transistor 21 to cause current 21 to flow across the source and drain of n-channel MOS transistor 21. In n-channel MOS transistor 22 as well, voltage V.sub.1 is applied to its gate to cause current I, which is one-half the current of current 2I, to flow across the source and drain. Current I also flows across the drain and source of n-channel MOS transistor 45. Since provision is made for a current mirror circuit that allows current of the same level to flow to p-channel MOS transistor 12 and p-channel MOS transistor 13, current 2I will also flow across the source and drain of p-channel MOS transistor 13.
The drain of n-channel MOS transistor 45 and the drain of n-channel MOS transistor 46 are both connected to the drain of n-channel MOS transistor 13, which operates as a constant-current source. Accordingly current I (2I-I=I) of the same level that flows to n-channel MOS transistor 45 flows to n-channel MOS transistor 46.
Assuming that n-channel MOS transistors 45 and 46 both operate in the transistor saturation range, the current flowing across the drain and source of each will be equal, realizing the following equation: EQU .beta..sub.45 /2.times.(V.sub.2 -VREF-.vertline.VT.sub.45.vertline.)=.beta..sub.46 /2.times.(V.sub.2 -.vertline.VT.sub.46.vertline.)
Were, .beta..sub.45 and .beta..sub.46 are the conductance coefficients of n-channel MOS transistors 45 and 46, respectively, and V.sub.2 is the drain voltage of p-channel MOS transistor 13.
If .beta..sub.45 and .beta..sub.46 are substantially equal, .vertline.VT.sub.46.vertline.-.vertline.VT.sub.45.vertline., which is the differential voltage of the threshold values of each of n-channel MOS transistors 45 and 46, is obtained as reference voltage VREF, which is the output from the source of n-channel MOS transistor 45. The value VREF depends solely on the difference between the threshold voltages of n-channel MOS transistor 45 and n-channel MOS transistor 46. As a result, the value of reference voltage VREF exhibits almost no change despite fluctuation in the threshold values of MOS transistors caused by external temperature or variation in the transistor threshold value when fabricating a semiconductor device.
A reference voltage generating circuit of the prior art, however, has the problem that only a particular fixed generated reference voltage VREF can be produced because the threshold values of n-channel MOS transistors 45 and 46 are fixed. Moreover, the reference voltage generating circuit of the aforementioned prior art also has the problem that variation in the characteristics of circuit elements at the time of fabrication results in variation in the obtained reference voltage, with the consequence that a reference voltage of a desired voltage cannot be obtained.